Förderjahr 2019 / Project Call #14 / ProjektID: 4501 / Projekt: Cloud_FPGA_tool
FPGAs have, at best, limited capabilities for introspecting or modifying the design in real time, making it extremely costly to locate and fix design errors once it is running on an FPGA.
Consequently, delivering reliable designs on schedule requires locating most errors before the design is deployed. This is done using several techniques, such as property testing and simulation.
Simulation is the most widespread verification method, and can be used in workflows familiar to software developers, such as unit and integration testing. nMigen includes a Python-based simulator that can be used to evaluate the behavior of any nMigen code. In addition, parts of the simulated hardware can be replaced with Python code, which can speed up the simulation or provide virtual I/O devices.
Although the nMigen Python-based simulator is powerful and seamlessly integrated with the language, it has a few inherent limitations: it cannot simulate third-party Verilog or VHDL code, and it is too slow to use on highly complex designs. To address this, we have developed CXXRTL, a Yosys backend that converts netlists into C++ code simulating their behavior.
Compared to existing solutions like Verilator, CXXRTL has several advantages: it is not tied to any specific hardware description language (community members have used CXXRTL to simulate mixed VHDL/Verilog designs); it is especially convenient to use from non-C++ languages through FFI mechanisms, such as Python's ctypes; it includes debug information, providing complete design visibility in debug builds and a high degree of visibility even in optimized builds. CXXRTL's performance approaches that of existing solutions.
CXXRTL forms the core of the new nMigen C++-based simulator. Although CXXRTL can simulate any hardware that can be implemented in nMigen much faster than the existing nMigen Python simulator, the need to use C++ is a significant barrier for Python developers. To remove this barrier, we are working on the nMigen C++-based simulator, which lets developers simulate nMigen code much faster through CXXRTL, but as seamlessly as with the existing Python-based simulator. Apart from the improved performance, the new simulator also makes it possible to reuse existing components written in VHDL, Verilog, or other languages supported by Yosys, and to implement virtual I/O devices in C++ using the full spectrum of platform-specific features.
Even though CXXRTL has been conceived for use in nMigen, it is not nMigen-specific in any way, and has received positive feedback from developers working with Verilog and VHDL alone. This is one way in which nMigen gives back to the open hardware community that makes it possible.